User Contributed MET/CAL PROCEDURE ============================================================================= INSTRUMENT: Genisco GFÿ8455-1:1.6kHz Highpass Filter DATE: 11-Apr-97 AUTHOR: User Contributed REVISION: 0 ADJUSTMENT THRESHOLD: 70% NUMBER OF TESTS: 27 NUMBER OF LINES: 162 CONFIGURATION: Datron 1281 CONFIGURATION: HP 3325A ============================================================================= STEP FSC RANGE NOMINAL TOLERANCE MOD1 MOD2 3 4 CON 1.001 ASK- P F 1.002 ASK+ X 1.003 IEEE [@1281]*RST 1.004 HEAD ÍÍ INITIAL CONDITIONS ÍÍ 1.005 DISP Connect the OUTPUT from the 3325A to the filter IN. 1.006 DISP Connect the filter OUT to the 1281 Hi/Lo INPUTS 1.006 DISP through a 50ê feedthrough. 1.007 HEAD {} 1.008 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 1.009 HEAD {º Filter Characteristics Test º} 1.010 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 1.011 HEAD ÍÍ Filter Characteristics Test ÍÍ 1.012 JMP 2.001 1.013 EVAL 2.001 IEEE [@1281]ACV AUTO 2.002 IEEE [@1281]DB_REF UNITY 2.003 IEEE [@1281]DB ON 2.004 IEEE [@1281]ACV FILT100HZ 2.005 IEEE [@3325]FU1,AM 1VR,FR 100HZ 2.006 IEEE [@1281]RDG?[D5000][T0][I] 2.006 IEEE [@1281]RDG?[T0][I] 2.007 MATH MEM1 = 0 2.008 MEME 2.009 MEMC D 100.000U 100H 3.001 IEEE [@3325]FU1AM1VRFR500HZ 3.002 IEEE [@1281]RDG?[D2000][I] 3.003 MATH MEM1 = 0 3.004 MEME 3.005 MEMC D 100.000U 500H 4.001 IEEE [@3325]FU1AM1VRFR1KH 4.002 IEEE [@1281]RDG?[D2000][I] 4.003 MATH MEM1 = 0 4.004 MEME 4.005 MEMC D 100.000U 1kH 5.001 IEEE [@3325]FU1AM1VRFR1.25KH 5.002 IEEE [@1281]RDG?[D2000][I] 5.003 MATH MEM1 = 0 5.004 MEME 5.005 MEMC D 100.000U 1.25kH 6.001 IEEE [@3325]FU1AM1VRFR1.4KH 6.002 IEEE [@1281]RDG?[D2000][I] 6.003 MATH MEM1 = 0 6.004 MEME 6.005 MEMC D 100.000U 1.4kH 7.001 IEEE [@3325]FU1AM1VRFR1.5KH 7.002 IEEE [@1281]RDG?[D2000][I] 7.003 MATH MEM1 = 0 7.004 MEME 7.005 MEMC D 100.000U 1.5kH 8.001 IEEE [@3325]FU1AM1VRFR1.6KH 8.002 IEEE [@1281]RDG?[D2000][I] 8.003 MATH MEM1 = 0 8.004 MEME 8.005 MEMC D 100.000U 1.6kH 9.001 IEEE [@3325]FU1AM1VRFR1.8KH 9.002 IEEE [@1281]RDG?[D2000][I] 9.003 MATH MEM1 = 0 9.004 MEME 9.005 MEMC D 100.000U 1.8kH 10.001 IEEE [@3325]FU1AM1VRFR2KH 10.002 IEEE [@1281]RDG?[D2000][I] 10.003 MATH MEM1 = 0 10.004 MEME 10.005 MEMC D 100.000U 2kH 11.001 IEEE [@3325]FU1AM1VRFR3KH 11.002 IEEE [@1281]RDG?[D2000][I] 11.003 MATH MEM1 = 0 11.004 MEME 11.005 MEMC D 100.000U 3kH 12.001 IEEE [@3325]FU1AM1VRFR4KH 12.002 IEEE [@1281]RDG?[D2000][I] 12.003 MATH MEM1 = 0 12.004 MEME 12.005 MEMC D 100.000U 4kH 13.001 IEEE [@3325]FU1AM1VRFR5KH 13.002 IEEE [@1281]RDG?[D2000][I] 13.003 MATH MEM1 = 0 13.004 MEME 13.005 MEMC D 100.000U 5kH 14.001 IEEE [@3325]FU1AM1VRFR7.5KH 14.002 IEEE [@1281]RDG?[D2000][I] 14.003 MATH MEM1 = 0 14.004 MEME 14.005 MEMC D 100.000U 7.5kH 15.001 IEEE [@3325]FU1AM1VRFR10KH 15.002 IEEE [@1281]RDG?[D2000][I] 15.003 MATH MEM1 = 0 15.004 MEME 15.005 MEMC D 100.000U 10kH 16.001 IEEE [@3325]FU1AM1VRFR15KH 16.002 IEEE [@1281]RDG?[D2000][I] 16.003 MATH MEM1 = 0 16.004 MEME 16.005 MEMC D 100.000U 15kH 17.001 IEEE [@3325]FU1AM1VRFR20KH 17.002 IEEE [@1281]RDG?[D2000][I] 17.003 MATH MEM1 = 0 17.004 MEME 17.005 MEMC D 100.000U 20kH 18.001 IEEE [@3325]FU1AM1VRFR35KH 18.002 IEEE [@1281]RDG?[D2000][I] 18.003 MATH MEM1 = 0 18.004 MEME 18.005 MEMC D 100.000U 35kH 19.001 IEEE [@3325]FU1AM1VRFR50KH 19.002 IEEE [@1281]RDG?[D2000][I] 19.003 MATH MEM1 = 0 19.004 MEME 19.005 MEMC D 100.000U 50kH 20.001 IEEE [@3325]FU1AM1VRFR75KH 20.002 IEEE [@1281]RDG?[D2000][I] 20.003 MATH MEM1 = 0 20.004 MEME 20.005 MEMC D 100.000U 75kH 21.001 IEEE [@3325]FU1AM1VRFR100KH 21.002 IEEE [@1281]RDG?[D2000][I] 21.003 MATH MEM1 = 0 21.004 MEME 21.005 MEMC D 100.000U 100kH 22.001 IEEE [@3325]FU1AM1VRFR200KH 22.002 IEEE [@1281]RDG?[D2000][I] 22.003 MATH MEM1 = 0 22.004 MEME 22.005 MEMC D 100.000U 200kH 23.001 IEEE [@3325]FU1AM1VRFR350KH 23.002 IEEE [@1281]RDG?[D2000][I] 23.003 MATH MEM1 = 0 23.004 MEME 23.005 MEMC D 100.000U 350kH 24.001 IEEE [@3325]FU1AM1VRFR580KH 24.002 IEEE [@1281]RDG?[D2000][I] 24.003 MATH MEM1 = 0 24.004 MEME 24.005 MEMC D 100.000U 580kH 25.001 IEEE [@3325]FU1AM1VRFR750KH 25.002 IEEE [@1281]RDG?[D2000][I] 25.003 MATH MEM1 = 0 25.004 MEME 25.005 MEMC D 100.000U 750kH 26.001 IEEE [@3325]FU1AM1VRFR1MH 26.002 IEEE [@1281]RDG?[D2000][I] 26.003 MATH MEM1 = 0 26.004 MEME 26.005 MEMC D 100.000U 1MH 27.001 HEAD {} 27.002 DISP {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 27.002 DISP {º THIS COMPLETES THE VERIFICATION º} 27.002 DISP {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 27.003 END